1. Field of the Invention
The present invention relates to the technical field of graphic processing and, more particularly, to a system and method for accelerating two-dimensional (2D) graphics in a computer system.
2. Description of Related Art
As shown in FIG. 1, a personal computer (PC) system typically comprises a processor 110, a north bridge 120, a system memory 130, a graphic chip 140, a video memory 150 and a display 160. The processor 110 executes a window operating system (OS) via the north bridge 120 and stores corresponding data in the system memory 130. Graphic data can be stored in the system memory 130 or the video memory 150. The graphic chip 140 performs graphical operations to decrease the computation load of the processor 110 and displays the graphic data stored in the video memory 150 on the display 160.
As shown in FIG. 2, the window operating system 210 transfers corresponding graphic commands to the 2D graphic device driver 230 by using a graphic device interface (GDI) 220. The 2D graphic device driver 230 sets the register content of the graphic chip 140 based on the graphic command transferred by the GDI 220. The hardware of the graphic chip 140 then performs graphic commands corresponding to the register content to accelerate execution of the graphic command.
The GDI 220 transfers ROP3 (Raster-Operation 3) graphic commands defined by the window operating system 210. Each ROP3 command performs a Boolean operation for source pixels (S), destination pixels (D) and a pattern (P). The source pixels (S) and the destination pixels (D) specify memory addresses corresponding to pixels in the system memory 130 or the video memory 150. For example, a command ROP3=0×BA(DPSnao) specifies a Boolean operation ‘[(NOT S) AND P] OR D’. That is, the source pixels (S) in the system memory 130 or the video memory 150 are processed by a NOT operation, then an AND operation with a pattern (P), and finally an OR operation with the destination pixels (D) in the system memory 130 or the video memory 150. The result is stored in the system memory 130 or the video memory 150 with respect to the destination pixels (D). When the 2D graphic device driver 230 receives a command ROP3=0×BA, the 2D graphic device driver 230 sets the corresponding registers of the graphic chip 140 based on the command ROP3=0×BA(DPSnao) and accordingly the hardware of the graphic chip 140 performs the NOT, AND and OR operations, and data transfer between memories. The delivery time between the GDI 220 and the 2D graphic device driver 230 for commands and parameters is minimized because a ROP3 graphic command includes all of the source pixel (S), destination pixel (D) and pattern (P) information. Furthermore, processing of graphical operations is accelerated by hardware and thus the processing time is greatly reduced.
The format of a typical command register for executing ROP3 commands by the graphic chip 140 is shown in FIG. 3. As shown, the format has fields to specify source pixel, destination pixel and pattern and color source (CS) information. However, the field for CS has only one bit, and thus it the field for CS is unable to distinguish whether the source pixel or pattern is colored. That is, the hardware of the graphic chip 140 can be utilized to accelerate the execution of corresponding graphic commands when only one of the source pixel or pattern is colored. If the source pixel and pattern are both colored, for example, the S and the P in the command ROP3=0×BA(DPSnao) are colored, the hardware of the graphic chip 140 cannot be utilized to accelerate the execution of graphic commands. Accordingly, one substitution is such that, the command ROP3=0×BA(DPSnao) having color source pixels and color pattern is divided by the 2D graphic device driver 230 into three ROP2 (Raster-Operation 2) commands: (1) (NOT S)>D1; (2) D1 AND P >D1; and (3) D1 OR D>D, and the hardware of the graphic chip 140 is activated to sequentially perform the three ROP2 commands. This increases the complexity of the 2D graphic device driver 230 and reduces the graphical processing speed due to the three ROP2 commands sequentially performed by the hardware of the graphic chip 140. Therefore, the conventional method for accelerating 2D graphics needs to be improved.